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136 lines
4.9 KiB
C
136 lines
4.9 KiB
C
/****************************************************************************
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*
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* Open Watcom Project
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*
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* Portions Copyright (c) 1983-2002 Sybase, Inc. All Rights Reserved.
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*
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* ========================================================================
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*
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* This file contains Original Code and/or Modifications of Original
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* Code as defined in and that are subject to the Sybase Open Watcom
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* Public License version 1.0 (the 'License'). You may not use this file
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* except in compliance with the License. BY USING THIS FILE YOU AGREE TO
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* ALL TERMS AND CONDITIONS OF THE LICENSE. A copy of the License is
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* provided with the Original Code and Modifications, and is also
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* available at www.sybase.com/developer/opensource.
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*
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* The Original Code and all software distributed under the License are
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* distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
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* EXPRESS OR IMPLIED, AND SYBASE AND ALL CONTRIBUTORS HEREBY DISCLAIM
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* ALL SUCH WARRANTIES, INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR
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* NON-INFRINGEMENT. Please see the License for the specific language
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* governing rights and limitations under the License.
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*
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* ========================================================================
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*
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* Description: definitions for code generator interface
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*
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****************************************************************************/
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#ifndef _CODEGEN_H_INCLUDED
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#define _CODEGEN_H_INCLUDED
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#define BIT_012 0x07
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#define BIT_345 0x38
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#define BIT_67 0xC0
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#define NOT_BIT_012 0xF8
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#define NOT_BIT_345 0xC7 /* mask to filter Mod- and R/M-bits for ModRM-byte */
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#define NOT_BIT_67 0x3F
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#define MOD_00 0x00
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#define MOD_01 0x40
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#define MOD_10 0x80
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#define MOD_11 0xC0
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/* opcode bits:
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* 0: w/ide bit, operand size BYTE <-> D/WORD
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* 1: s/ign bit, sign extended immediate
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* 1: d/irection bit
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*/
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#define W_BIT 0x01
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#define NOT_W_BIT 0xFE
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#define ADRSIZ 0x67
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#define OPSIZ 0x66
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#define OP_WAIT 0x9B
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#define EXTENDED_OPCODE 0x0F
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#define OP_NOP 0x90
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#define RM_BX_SI 0x00
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#define RM_BX_DI 0x01
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#define RM_BP_SI 0x02
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#define RM_BP_DI 0x03
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#define RM_SI 0x04
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#define RM_DI 0x05
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#define RM_BP 0x06
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#define RM_BX 0x07
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#define RM_SIB 0x04
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#define RM_D32 0x05 /* direct 32 */
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#define RM_D16 0x06 /* direct 16 */
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#define SCALE_FACTOR_1 0x00
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#define SCALE_FACTOR_2 0x40
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#define SCALE_FACTOR_4 0x80
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#define SCALE_FACTOR_8 0xC0
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#define FPE_MIN 0xD8
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#define FPE_MAX 0xDF
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#define IS_MEM_TYPE( op, typ ) ( (op) == MT_##typ || (op) == MT_S##typ )
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#define IS_MEMTYPE_SIZ( op, siz ) ( ( ( (op) & MT_SPECIAL_MASK ) < MT_SPECIAL ) && ( ( (op) & MT_SIZE_MASK ) == ( siz - 1 ) ) )
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/*
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* values for <byte1_info>
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* 000 : the first byte is opcode, follow by rm_byte
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* F_16 : the first byte is OPSIZ prefix if in use32 segment
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* F_32 : the first byte is OPSIZ prefix if in use16 segment
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* F_0F : the first byte is 0x0F, follow by opcode and rm_byte
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* the entries must be sorted related to F_0F prefix:
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* entries < F_0F emit NO 0F prefix, entries >= F_0F emit one.
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* v2.06: magnitude of this field extended to 8 (previously 4).
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* the entries with 38/3A must be last in the 0F group!
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*/
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enum byte1_info {
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F_16 = 1, /* 16bit variant, 66h switches */
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F_32, /* 32bit variant, 66h switches */
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F_16A, /* 16bit variant, 67h switches */
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F_32A, /* 32bit variant, 67h switches */
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F_F3, /* F3 prefix (pause: F3 90) */
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#if AMD64_SUPPORT
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F_48, /* REX.W prefix */
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#endif
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F_0F = 16, /* 0F escape */
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F_0F0F, /* AMD 3DNow "prefix" */
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F_660F, /* SSEx prefix 1 */
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F_F20F, /* SSEx prefix 2 */
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F_F30F, /* SSEx prefix 3 */
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F_0FNO66, /* 0F escape, no size prefix */
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#if AMD64_SUPPORT
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F_480F, /* REX.W + 0F prefix ( cmpxchg16b ) */
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#endif
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F_0F38, /* must be first of 38/3A variants */
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F_0F3A,
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F_660F38,
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F_660F3A,
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F_F20F38,
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};
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#if AVXSUPP
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/* VX_NND is only needed if instruction has more than 2 operands */
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enum vex_info {
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VX_L = 0x01, /* VEX.L supported */
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VX_NND = 0x02, /* VEX.NDS/NDD not supported */
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VX_DST = 0x04, /* VEX.NDD (if op3 is an immediate) */
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VX_IMM = 0x08, /* no VEX.NDS if op3 is an immediate */
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VX_NMEM = 0x10, /* no VEX.NDS if op1 is a mem ref (vmovs[d|s], vmov[h|l]p[d|s] ) */
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VX_HALF = 0x20, /* op2 is half-sized */
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};
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#endif
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extern ret_code codegen( struct code_info *, uint_32 );
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#endif
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